In a semiconductor package in related art, a package substrate has a central processing unit (CPU) disposed thereon. One of semiconductor package structures is a ball grid array (BGA). To mount a BGA semiconductor package over a printed circuit board, reflow is conducted.
After the reflow, however, a solder ball on the package substrate may be separated from the printed circuit board, or a plurality of solder balls may be in contact with each other, causing a short circuit. That is, faulty connections may occur after the reflow. The larger the package substrate is, the more noticeable these faulty connections are.
Japanese Laid-open Patent Publication No. 11-163043 and Japanese Laid-open Patent Publication No. 5-327159 are examples of related art.